In a First In First Out (FIFO) memory, data entered at the input appear at the output in the same order. Input and output in a FIFO are typically controlled by two separate clocks. FIFO's are typically used for buffering data. Some FIFO's are based on random access memory (RAM) technology, which is susceptible to both short term and long term errors.
In existing systems that employ FIFO memory elements, either no error checking of data flowing through the FIFO is provided, or a simple parity check of bits on a per word basis is used. With parity checking, when a data word is output from the FIFO, the parity of the data word is checked against an expected value (i.e., even or odd). If the data word does not match the expected parity value, an error is determined to have occurred. Although this method works for determining single bit errors, it does not always work well for determining multiple bit errors.
It is desirable to provide a more robust system for detecting data corruption in data streams passing through FIFO memory elements.